The present invention generally relates to semiconductor circuits, and, more particularly, to a semiconductor circuit having an improved layout pattern.
The present invention especially relates to the layout pattern of a semiconductor circuit which is employed when arranging buffers on a substrate together with 2-row type unit cells which form an ASIC (Application Specific Integrated Circuit). The buffers are used to drive signal lines such as clock signal lines which have a large load within an LSI (Large Scale Integrated) circuit which forms the ASIC, or signal lines of a MCM (Multi Chip Module) which forms the ASIC.
From the point of view of the design technique, the ASIC can be categorized into semi-customized ICs which are made by automatic designing, and full-customized ICs which are made by manual designing. The semi-customized ICs employ the gate array system or the standard cell system, in both of which systems a large portion of the IC is formed by 2-row type unit cells. Each 2-row type unit cell is the minimum combination required to form a unit cell. The 2-row type unit cell is made up of 1-row type cells which are arranged in 2 rows, where each 1-row type cell has a p-channel transistor and an n-channel transistor.
Generally, when designing the ASIC, it is important that the layout pattern satisfies the following conditions which are: (i) the unit cell is easy to form and the wiring is accordingly easy to form; (ii) a large number of unit cells can be formed within the chip.
The condition (i) is satisfied by employing the 2-row type unit cell described above. On the other hand, whether or not the condition (ii) can be satisfied depends on how small the transistor width of the unit cell can be made and how narrow the interval of the unit cells can be made in the chip layout pattern. The minimum interval of the metal wiring is prescribed by the mask design rules. In addition, the wiring within the unit cell utilizes a wiring region which is formed on an upper layer above the transistor. For this reason, the wiring channel on the transistor decreases if the transistor width is decreased, thereby making it difficult to form the unit cell. Accordingly, the transistor width is selected to an appropriate minimum value within a range such that various unit cells can be formed, for both the p-channel and n-channel transistors.
FIG.1 shows an example of a layout pattern of 2-row type unit cells which are realized by taking the above into consideration. In FIG. 1, a power supply line 1 supplies a power supply voltage V.sub.DD, and a power supply line 2 supplies a power supply voltage V.sub.SS. The transistors in the layout pattern include p-channel transistors 5 and n-channel transistors 6. A width W.sub.P of the p-channel transistor 5 and a width W.sub.N of the n-channel transistor 6 are selected such that W.sub.P =W.sub.N.
The interval of the unit cells can recently be made narrower than before by employing the so-called over-cell-routing technique, and it has become possible to further improve the integration density of the IC. According to this over-cell-routing technique, the wiring channel is used for the wiring of the chip layout pattern if the wiring channel exists on the upper layer of the unit cell.
However, although the layout pattern shown in FIG. 1 realizes the improved integration density, the transistor widths W.sub.P and W.sub.N of the p-channel and n-channel transistors 5 and 6 are set to the minimum values and are set equal to each other. For this reason, a difference is introduced between the driving capabilities of the p-channel and n-channel transistors 5 and 6. In other words, if the transistors have the same size, the n-channel transistor 6, which uses the electrons having a small effective mass as the carriers, has a larger mobility compared to the p-channel transistor 5, which uses the holes having a large effective mass as the carriers.
The difference between the driving capabilities similarly affects a buffer which is made up of the p-channel and n-channel transistors. For this reason, if a signal line is driven by a buffer which is made up of the p-channel and n-channel transistors having the same transistor width, a time T.sub.rise required for the signal waveform to rise and a time T.sub.fall required for the signal waveform to fall become different due to the difference between the driving capabilities of the p-channel and n-channel transistors. For example, T.sub.rise &gt;T.sub.fall as shown in FIG. 2. This difference between the times T.sub.rise and T.sub.fall does not cause a serious problem if the signal line within the LSI to be driven has a relatively small load. However, if this buffer is used to drive a clock signal line within the LSI having a large load or to drive a signal line of a MCM, the difference between the times T.sub.rise and T.sub.fall causes problems, such as a change in the duty ratio of the pulses, thereby making it difficult to design the system.
In order to avoid the above described problems, it is known from experience that the transistor width of the p-channel transistor should be made two times the transistor width of the n-channel transistor if the p-channel and n-channel transistors are to have the same driving capability. For example, the layout pattern in this case becomes as shown in FIG. 3 or FIG. 4. In FIGS. 3 and 4, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted.
According to the layout patterns shown in FIGS. 3 and 4, a buffer BF is arranged to use the power supply lines 1, 1, 2 and 2 in common with 2-row type unit cells UC. In the case of the layout pattern shown in FIG. 3, the width of a p-channel transistor 7 is extended in a vertical direction Y by a certain distance, so that the width of the p-channel transistor 7 is two times the width W.sub.N of an n-channel transistor 8. On the other hand, in the case of the layout pattern shown in FIG. 4, the length of the p-channel transistor 7 is extended in a horizontal direction X by a certain distance, so that the length of the p-channel transistor 7 is two times the length of the n-channel transistor 8. By using the layout pattern shown in FIG. 3 or FIG. 4, the rise time T.sub.rise of the signal waveform which is driven by the buffer BF becomes approximately equal to the fall time T.sub.fall of the signal waveform, as shown in FIG. 5.
However, in the layout pattern shown in FIG. 3, the p-channel transistor 7 is merely extended in the vertical direction Y, and the width of the p-channel transistor 7 in the vertical direction Y becomes two times that of the p-channel transistor 5 forming the unit cell UC. As a result, a portion of the p-channel transistor 7 projects a distance H in the vertical direction Y from the power supply line 1. This projecting portion interferes with the narrowing of the interval between the unit cells UC, and introduces a new problem in that the integration density of the entire LSI deteriorates.
On the other hand, in the layout pattern shown in FIG. 4, the p-channel transistor 7 is merely extended in the horizontal direction X, and the length of the p-channel transistor 7 in the horizontal direction X becomes two times that of the p-channel transistor 5 forming the unit cell UC. As a result, an unused region R is formed under the p-channel transistor 7 in the vertical direction Y. This unused region R has a size which is approximately two times that of the n-channel transistor 6 forming the unit cell UC. Because the buffer for driving the clock signal line or the signal line of the MCM needs to have a large size compared to the buffer for driving the wiring within the LSI, the existence of such an unused region R is not negligible from the point of view of improving the integration density of the LSI, and deteriorates the integration density.